The mask logic also controls the selected operational registers for determining what portions of the words of numeric data stored in the operational registers are to be operated on arithmetically by the arithmetic unit or to be exchanged during data exchange operations.ġ. Thus the instruction word decoder logic decodes instructions for operating selected ones of the plurality of operational registers to effect arithmetic operations by coupling selected operational registers to the arithmetic unit or data exchange operations by coupling selected operational registers together. The instruction word decoder logic includes mask logic for generating mask signals to the plurality of operational register selector gates. The system further preferably includes a plurality of operational registers for storing numeric data received from the input or outputted by the arithmetic unit and a plurality of operational register selector gates coupling the operational registers with the arithmetic unit or with each other.
An electronic calculator or microprocessor system of the type preferably having keyboard input and a visual display is implemented with a semiconductor chip having an arithmetic unit, an address register responsive to the input, an instruction word memory for storing a number of instruction words and addressable by the address register, and instruction word decoder logic for decoding the instruction words and for controlling the arithmetic unit in response thereto.
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